This application is based on Japanese Patent Application 2000-093672, filed on Mar. 28, 2001, the entire contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to semiconductor devices and their manufacture methods, and more particularly to semiconductor techniques of forming different elements on the same substrate, the elements including DRAM memory cells and SRAM memory cells with MOSFET""s, and analog capacitors and flash memories.
b) Description of the Related Art
In this specification, an offset insulating film is intended to mean an insulating film (cap layer) formed on a conductive layer and having the same shape as viewed in plan as that of the conductive layer. The conductive layer may have a multi-layer structure or the offset insulating film may have a multi-layer structure. In this specification, the terms xe2x80x9clamination structurexe2x80x9d or xe2x80x9clamination structural bodyxe2x80x9d are intended to mean a structural body including a lamination structure (structural body) of an electrode and an insulating film such as an offset film formed on the electrode. An element region is intended to mean a region containing at least one active region therein. The principal surface of a semiconductor substrate is a two-dimensional surface and its surface irregularity such as concave and convex poses almost no practical problem. A xe2x80x9cheightxe2x80x9d is intended to mean a height measured from such a two-dimensional surface along a direction normal to the surface.
Recent large scale of semiconductor integration circuits requires micro-fine semiconductor elements. In order to realize a semiconductor integrated circuit having gate electrodes, wirings and contact holes more smaller in size, resolution of photolithography has been improved heretofore by using exposure light of a shorter wavelength.
Device structures have been studied which can reduce a minimum image resolution size as well as a position alignment margin between lithography processes. As one example of such device structures, a self-align contact (hereinafter called SAC) structure is known.
FIG. 7 is a cross sectional view showing the outline structure of SAC.
As shown in FIG. 7, an element isolation region 501 is defined in a silicon substrate 500. A number of lamination structural bodies G1 are formed on the silicon substrate 500 on the element isolation region 501 and in an area away from the region 501 by some distance. The lamination structural body G1 is formed on a gate insulating film 503 and has the lamination structure made of a gate electrode layer 505, a barrier metal layer 507 and an offset insulating film 511. In the following description, a lamination of the gate electrode layer 505, barrier metal layer 507 and offset insulating film 511 is called the lamination structural body G1. Spacer films (side wall insulating films) 515 are formed on the side walls of the lamination structural body G1.
Contact holes are formed between mutually adjacent lamination structural bodies G1, being sandwiched between the spacer films 515 formed on the side walls of the lamination structural bodies G1. In each contact hole, a plug electrode 521 of doped amorphous silicon is formed. The bottom surface of the plug electrode 521 is in contact with the surface of the silicon substrate 500. The plug electrode 521 connects together, for example, an upper structure to be formed above the lamination structural body G1 and a lower structure to be formed in the silicon substrate 500.
The upper surface of the plug electrode 521 can be made generally flush with the upper surface of the offset insulating film 511, for example, by a chemical mechanical polishing (CMP) method.
If SAC techniques are incorporated, the plug electrode 521 can be formed in a self alignment manner between adjacent lamination structural bodies G1. A position alignment margin can therefore be increased between a contact hole forming process and a plug electrode forming process.
With developments on semiconductor integrated circuit techniques, it is possible to realize a so-called system LSI in which one or more systems are formed in one semiconductor chip by forming various types of integrated circuits. A system LSI has various types of IC""s formed therein, including a logic IC cell part, a memory cell part (such as dynamic random access memory (DRAM), static random access memory (SRAM) and flash memory), an analog cell part and the like. In order to form such various IC""s and reduce an area occupied by these IC""s, SAC techniques are becoming more and more important. It is an important point that micro-fineness and high reliability of a system LSI rely on how the heights of upper surfaces of offset insulating films are made flush in respective IC""s in the silicon substrate plane.
Problems which occur when a memory cell part and an analog cell part are formed on the same substrate will be described with reference to FIGS, 8A to 8E, by taking as examples a DRAM cell part and an analog capacitor part.
As shown in FIG. 8A, first and second element regions 400a and 400b are defined in a silicon substrate 400. In the first element region 400a, a DRAM cell part is formed having a number of lamination structural bodies (word lines) G1. The structure of the DRAM cell part is similar to the SAC structure shown in FIG. 7. In the second element region 400b, an analog capacitor part is formed having an analog capacitor element Cp.
A gate oxide film 403 is formed on the surface of the first element region 400a. On the gate oxide film 403, a first lamination structural body G1 is formed including a lamination of a gate electrode layer 405a, a barrier metal layer 407a and an offset insulating film 411a. Spacer films (side wall insulating films) 415a are formed on the side walls of each lamination structural body G1.
The analog capacitor element Cp formed in the second element region 400b includes a lower electrode 430, a dielectric layer 429 and a second lamination structural body. The second lamination structural body has a three-layer structure including an upper electrode 405b, a barrier metal layer 407b and an offset insulating film 411b. Spacer films 415b are formed on the side walls of the lower electrode 430, dielectric layer 429 and second lamination structural body. The gate electrode layer 405a, barrier metal layer 407a and offset insulating film 411a are formed by the common layers to those of the upper electrode 405b, barrier metal layer 407b and offset insulating film 411b. 
The height of the upper surface of the offset insulating film 411b in the analog capacitor part as measured from the upper surface of the silicon substrate 400 is higher than the height of the upper surface of the offset insulating film 411a in the DRAM cell part by an amount corresponding to a thickness of the lower electrode 430 and dielectric layer 429 (both collectively called a lower structure).
Interlayer insulating films 410a and 410b are formed over the silicon substrate 400, covering the lamination structural bodies G1 and analog capacitor element Cp and having the etching characteristics different from the offset insulating films 411a and 411b. Although the interlayer insulating film 410a is formed in the first element region 400a and the interlayer insulating film 410b is formed in the second element region 400b, these interlayer insulating films are made of the same layer. The upper surface of the interlayer insulating film 410a is lower than the upper surface of the interlayer insulating film 410b. Under the etching conditions that the interlayer insulating films can be selectively etched relative to the offset insulating films, the interlayer insulating films 410a and 410b are polished from their upper surfaces by CMP. CMP automatically stops when the upper surface of the offset insulating film 411b is exposed.
As shown in FIG. 8B, the upper surfaces of the interlayer insulating films 410a and 410b are generally flush in the first and second element regions 400a and 400b. 
As shown in FIG. 8C, a resist mask 435 is formed covering the second element region 400b and a partial area of the first element region 400a although not shown in FIG. 8C. The resist mask 435 has an opening in the first element region 400a shown in FIG. 8C, the opening extending along a direction in parallel to the drawing sheet. By using the resist mask 435 as an etching mask, the interlayer insulating film 410a in the first element region 400a is etched. Contact holes 440 are therefore formed between the lamination structural bodies G1, reaching the surface of the silicon substrate 400. The resist mask 435 is thereafter removed.
As shown in FIG. 8D, impurity doped amorphous silicon layers 431a and 431b are deposited in the first and second element regions 400a and 400b to a height higher than the upper surfaces of the lamination structural bodies G1 and analog capacitor element Cp. The amorphous silicon films 431a and 431b are polished by CMP or the like from the upper surfaces thereof. CMP stops when the upper surface of the offset insulating film 411b is exposed. As shown in FIG. 8E, the amorphous silicon film 431a is left on the offset insulating films 411a. The amorphous silicon film 431a for plug electrodes cannot be electrically separated by the lamination structural bodies G1 in the first element region 400a and the SAC structure cannot be formed.
Such a phenomenon occurs when elements having the SAC structure and elements whose upper surfaces are different in height from those of the offset insulating films of the SAC structure are formed on the same substrate.
It is an object of the present invention to provide semiconductor techniques of forming on the same substrate, elements having the SAC structure and elements whose upper surfaces are different in height from those of offset insulating films of the SAC structure, before a plug electrode forming process.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having first and second regions defined in a principal surface of said semiconductor substrate; a first lamination structure formed in a partial area of said first region of the principal surface of said semiconductor substrate, said first lamination structure having a conductive film and an insulating film stacked in this order from the side of the semiconductor substrate; a first underlying film formed in said second region of the principal surface of said semiconductor substrate; and a second lamination structure formed on said first underlying film and having a conductive film and an insulating film stacked in this order from the side of said semiconductor substrate, said insulating films of said first and second lamination structures being made of same material and a height of an upper surface of said second lamination structure as measured from the principal surface of said semiconductor substrate being equal to or lower than a height of an upper surface of said first lamination structure as measured from said principal surface of said semiconductor substrate.
The upper surface of the first lamination structure of the semiconductor device is an uppermost surface.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of: (a) preparing a semiconductor substrate with first and second regions being defined in a principal surface of said semiconductor substrate; (b) forming a first underlying film in said second region of said semiconductor substrate; (c) forming a first conductive film on said first region and said first underlying film; (d) forming a first insulating film on said first conductive film; (e) patterning at least two layers including said first conductive film and said first insulating film to leave a first lamination structure on said semiconductor substrate in said first region and a second lamination structure on said first underlying film in said second region, said first lamination structure being made of a portion of said first conductive film and a portion of said first insulating film stacked one upon the other, and said second lamination structure being made of a portion of said first conductive film and a portion of said first insulating film; and (f) thinning said second lamination structure so that an upper surface of said second lamination structure becomes flush with or lower than an upper surface of said first lamination structure.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising steps of: (a) preparing a semiconductor substrate with first and second regions being defined in a principal surface of said semiconductor substrate; (b) forming a first underlying film in said second region of said semiconductor substrate; (c) forming a first conductive film on said first region and said first underlying film; (d) forming a first insulating film on said first conductive film; (e) thinning said first insulating film in said second region so that an upper surface of said first insulating film in said second region becomes flush with or lower than an upper surface of said first insulating film; and (f) patterning at least two layers including said first conductive film and said first insulating film to leave a first lamination structure on said semiconductor substrate in said first region and a second lamination structure on said first underlying film in said second region, said first lamination structure being made of a portion of said first conductive film and a portion of said first insulating film stacked one upon the other, and said second lamination structure being made of a portion of said first conductive film and a portion of said first insulating film.
According to the semiconductor device manufacture methods, the upper surface of said first lamination structure can be made an uppermost surface.
According to a further aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of: (a) preparing a semiconductor substrate with first and second regions being defined in a principal surface of said semiconductor substrate; (b) forming a first underlying film in said second region of said semiconductor substrate; (c) forming a first conductive film on said first region and said first underlying film; (d) forming a first insulating film on said first conductive film; (e) patterning at least two layers including said first conductive film and said first insulating film to leave a first lamination structure on said semiconductor substrate in said first region and a second lamination structure on said first underlying film in said second region, said first lamination structure being made of a portion of said first conductive film and a portion of said first insulating film stacked one upon the other, and said second lamination structure being made of a portion of the first conductive film and a portion of said first insulating film; (f) forming an interlayer insulating film on said principal surface of said semiconductor substrate, said interlayer insulating film covering said first and second lamination structure; (g) thinning said interlayer insulating film until an upper surface of said second lamination structure is exposed, under a first thinning condition that a ratio of a thinning speed of said first insulating film to a thinning speed of said interlayer insulating film is larger than 1; and (h) thinning said interlayer insulating film and said second lamination structure until an upper surface of said first lamination structure is exposed, under a second thinning condition without selectivity.
According to the semiconductor device manufacture method, the upper surfaces of said interlayer insulating film and second lamination structure can be made flush with the upper surface of said first lamination structure.
According to the semiconductor techniques of the invention, even if the heights of offset insulating films are different in the same substrate, said upper surface of said interlayer insulating film can be made flush with the upper surface of said offset insulating film. Even if contact plugs are formed by polishing, adjacent plugs are prevented from being electrically shorted. It is particularly effective for SAC structures wherein openings of a plug pattern are near at gate electrodes.